The present invention relates to a method of driving a plasma display. More particularly, the present invention relates to a method of driving a plasma display in which each display frame comprises plural subframes and the gradation display is attained by the combination of the lit subframes.
The plasma display (PD) apparatus has good visibility because it generates its own light, is thin and can be made with a large-screen and high-speed display and, therefore, it is attracting interest as a replacement for the CRT display.
FIG. 1 is a diagram that shows the basic structure of a PD apparatus.
As shown in FIG. 1, in a plasma display panel (PDP) 10, X electrodes (the first electrode: sustain electrode) X1, X2, . . . , and Y electrodes (the second electrode: scan electrode) are arranged adjacently by turns and address electrodes (the third electrode) A1, A2, . . . are arranged in the direction perpendicular to that of the X and Y electrodes. A display line is formed between a pair of the X electrode and the Y electrode, that is, between X1 and Y1, X2 and Y2, and so on, and a display cell (hereinafter simply referred to as cell) is formed at the point where a display line and an address electrode intersect.
The X electrodes are commonly connected to an X sustain circuit 14, and the identical drive signal is applied to them. The Y electrodes are individually connected to a Y scan driver 12 and a scanning pulse is applied sequentially to them in the address action, which will be described later or, otherwise, the identical drive signal is applied by a Y sustain circuit 13. The address electrodes are connected to an address driver 11 and an address signal to select an ON cell and an OFF cell, in synchronization with the scanning pulse in the address action or, otherwise, the identical drive signal is applied to them. A control circuit 15 outputs a signal that controls each above-mentioned part.
FIG. 2 is a diagram that shows the structure of a frame to describe the drive sequence in the PDP apparatus. Since the discharge of the plasma display has only two states, that is, the ON state and the OFF state, the gradation of display is represented by the number of times of light emission. Therefore, a frame corresponding to a display is divided into plural subfields as shown in FIG. 2. Each subfield comprises the reset period, address period, and the sustain period. In the reset period, an action is carried out that brings all the cells, regardless whether the cell was ON or OFF in the preceding field, into a uniform state, for example, a state in which wall charges are eliminated or wall charges are formed uniformly. In the address period, a selective discharge (address discharge) is carried out in order to determine whether a cell is in the ON or OFF state according to the display data and wall charges needed to cause a discharge for light emission to occur in the subsequent sustain period are formed on a cell in the ON state. In the sustain period, a discharge is carried out repeatedly for light emission in the cell put into the ON state in the address period. The length of the sustain period, that is, the number of times of light emission differs from subfield to subfield, and the gradation of display can be represented by setting the numbers of times of light emission to a ratio of, for example, 1:2:4:8 . . . , and combining subfields to emit light for each cell according to the gradation.
FIG. 3 is a waveform chart that shows an example of the conventional method of driving a plasma display panel. As shown schematically, in the reset period, a pulse of the voltage Vw greater than the discharge start voltage, 300 V for example, is applied to the X electrode. The application of this pulse causes a discharge to occur in every cell regardless whether the cell was ON or OFF in the preceding subfield and wall charges are formed. When this pulse is removed, a discharge is caused to occur again by the voltage due to the wall charges themselves, and because there is no potential difference between electrodes, the space charges generated by the discharge are neutralized and a uniform state without a wall charge is realized. In the address period, a scanning pulse is applied sequentially to the Y electrode and an address pulse (address signal) is applied to the address electrode of the cell to be lit of the display line to cause a discharge to occur. This discharge propagates to the X electrode side and wall charges are formed between the X electrode and the Y electrode. This scanning is performed to the entire display line. In the address period, it is required that a discharge is caused to occur in the cell to which an address pulse is applied, and not in the cell to which an address pulse is not applied, and the voltage of the address pulse is determined with various error factors being taken into account. Then, in the sustain period, a sustaining pulse of the voltage Vs (approx. 170 V) is applied repeatedly to the X electrode and the Y electrode. When the sustaining pulse is applied, the cell in which wall charges are formed in the address period takes place a discharge because the voltage due to the wall charges is superposed on that of the sustaining pulse and the total voltage exceeds the discharge start voltage. The cell, in which no wall charge is formed in the address period, does not discharge. Although almost all charges are neutralized, a certain amount of ions and metastable atoms remains in the discharge space. It may be a case in which these remaining charges are used to act as a priming to cause an address discharge without fail for the next address discharge. This is called, in general, the pilot effect or the priming effect.
FIG. 4 is a diagram that shows another example of a conventional driving method disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2000-75835 by the present applicant. This driving method can cause a weak reset discharge to occur and prevent the contrast from deteriorating due to the reset discharge by designing the reset pulse with a slope waveform in which voltage changes gradually. In addition, Japanese Unexamined Patent Publication (Kokai) No.2000-75835 has disclosed that it is possible to make an amount of wall charges accumulate by adjusting the voltage applied between the X electrode and the Y electrode when the reset period is completed, and it is also possible to cause a stable address discharge to occur by setting the voltage with the slope waveform to be applied to the Y electrode to a voltage between the voltage when the scanning pulse is not applied and that of the scanning pulse in the address period.
The basic structure and action of the plasma display apparatus are described as above, but various examples of modification have been proposed. In one of the modifications, for example, plural subfields with the same number of times of light emission are provided in the frame structure as shown in FIG. 2 to make an animation display smooth. In another modification, a reset action accompanied by write discharge is carried out only in the first subfield of a frame and not in the reset action of the subsequent subfields. In another modification, a reset is carried out not in all the cells but only in the cells that were ON in the preceding subfield. In another modification, uniform wall charges are left in the reset action and the erasing address method may be used to select cells that are OFF to eliminate wall charges in the address action. In another modification, a desired amount of charges is left to be utilized in the address action by applying a voltage between the X electrode and the Y electrode from which the reset pulse is removed. Moreover, the present applicant has disclosed the plasma display apparatus employing a method called the ALIS method, in which the number of display lines is doubled without changing the number of the X electrode and the Y electrode by forming display lines in every slit between the X electrode and the Y electrode, that is, between each Y electrode and both X electrodes on both sides, in EP 0 762 373 A2.
As explained so far, there are various modifications of the plasma display apparatus, and the present invention can be applied to every one of them.
A high quality display, which exceeds that of a CRT, is required of the plasma display apparatus. The factors that will realize the high quality of display include the high definition, the high gradation, the high brightness, the high contrast, and so on. To achieve a high definition, it is necessary to increase the numbers of display lines and display cells by narrowing the pixel pitch, and the above-mentioned ALIS method has a structure that enables the realization of a high definition at a low cost. To achieve a high contrast, it is necessary to decrease the intensity and the number of times of discharges of such as the reset pulse, which has no relation to the display.
To achieve a high gradation, it is necessary to increase the number of subfields in the frame to increase the number of gradations that can be represented, but this also requires that the time required for the reset action and the address action be abbreviated or the period of the sustaining discharge be abbreviated. To achieve a high brightness, it may be a measure that the intensity of a sustaining discharge is increased, but this will lead to a problem in that the fluorescent materials are degraded. Another measure may be that the number of times of sustaining discharge in the frame is increased. To increase the number of times of sustaining discharge, it is necessary to abbreviate the period of sustaining discharge or increase the ratio of the sustaining period by abbreviating the time required for the reset action and the address action as described above. The abbreviation of the sustaining action period is, however, has its own limit in the current structure because a stable occurrence of sustaining discharge must be maintained. Therefore, from the viewpoint of the higher gradation and brightness, the abbreviation of time of the reset action and the address action is required. Particularly, the address period is longer than the reset period because a scanning pulse is applied sequentially, therefore, if the scan pulse can be narrowed, the effect resulting from the reduction of time will be large.
The voltage between the address electrode and the Y electrode in the address action is the difference in voltage between the address pulse and the scanning pulse (or the voltage added by the effective voltage due to the wall charges formed in the reset period), and a discharge is caused to occur when the effective voltage exceeds the discharge threshold voltage. If the difference between this effective voltage and the discharge threshold voltage is large, the width of the scanning pulse can be made narrow because the time lag before the address discharge is short and, if the difference is small, the width of the scanning pulse needs to be widened because the time lag before the address discharge is long. That is, the relation between the effective voltage between the address electrode and the Y electrode and the width of the scanning pulse is a trade-off. Therefore, one method to cause the action with a narrow scanning pulse is to increase the difference in voltage between the address pulse and the scanning pulse.
Taking various error factors into account, it is necessary to determine the voltage of address pulse so that an address discharge is caused to occur in the cell to which an address pulse is applied, and not in the cell to which an address pulse is not applied. More concretely, the voltage of address pulse is set to a voltage greater than the variations of the effective voltage to be applied to each cell, and the voltage of scanning pulse (and the effective voltage due to the wall charges formed in the reset period) is determined so that the discharge threshold voltage is reached when the half of the voltage of address pulse is applied. The scanning pulse depends largely on the voltage difference from that of the address pulse, and if the address pulse has a positive polarity, the scanning pulse has a negative polarity. As described above, it is necessary, for example, to decrease the voltage of the scanning pulse to increase the difference voltage, but in this case, a problem relating to the pressure tightness of the Y electrode is brought forth.
Therefore, it may be recommended to leave wall charges effective for the next address action in the reset period so that the voltage difference between the address pulse and the scanning pulse is increased effectively by utilizing the voltage due to the residual wall charges.
Taking the above-mentioned points into account, the voltage of address pulse, the voltage and the width of scanning pulse, and the amount of the wall charges to be left in the reset period are determined so that the address discharge according to the display data takes place without fail.
In the plasma display apparatus, a subframe structure as shown in FIG. 2 is provided to represent gradation, and subframes to be put into the ON state according to the display level are selected for each cell. Generally, the conditions about the voltage of address pulse, the voltage and the width of scanning pulse, and the amount of wall charges to be left in the reset period used to be identical in all the subframes.
If, however, the identical conditions are provided for each subframe in the reset period and the address period, the time lag before the occurrence of address discharge differs from subframe to subframe. This time lag before the occurrence of address discharge is caused because the priming effect is not sufficient, and address discharge is made more unlikely to take place. As described above, the charges generated by the discharge are accumulated as wall charges or are neutralized, but a certain amount of ions and metastable atoms remains in the discharge space, providing the priming effect. The charges in the discharge space are generated according to the intensity of the discharge and are neutralized gradually and disappear. Therefore, in the case where a largely-weighted subframe is lit, the priming effect with a considerable magnitude can be expected because of many sustain discharges, but when a slightly-weighted subframe is lit, the priming effect appears only slightly because the number of times of sustaining discharge is small. Moreover, the priming effect dwindles, after the discharge, as time goes by. Therefore, in the case where the period of dark display is long, the priming effect of the subframe is small because only slightly-weighted subframes in each frame are lit, dwindles because there is no subframe to be lit until the next frame, and becomes very small by the time of the address period of the subframe in the next frame, and the address discharge is made more unlikely to take place.
Conventionally, the conditions of the voltage of the address pulse, the voltage and the width of the scanning pulse, the amount of the wall charges to be left in the reset period, and so on, used to be determined in order to cause the address action to take place without fail even in such case. Because the difference in each frame increases the variations in the effective voltage in the address action, the voltage of the address pulse used to be increased or the width of the scanning pulse used to be widened accordingly to increase the range of allowance. It is, however, necessary to employ an address driver of high voltage resistance when the voltage of the address pulse is increased, and this will result in a problem that the cost is raised. On the other hand, when the width of scanning pulse is widened, a problem in that the address period is lengthened is brought forth.
As described above, such method that satisfies both conditions that the voltage of the address pulse is lowered and that the width of the scanning pulse is narrowed has not been employed until now.
The object of the present invention is to realize a method of driving a plasma display in which a discharge is caused to occur without fail for the address action even if the voltage of the address pulse is low and the width of the scanning pulse is narrow.
The method of driving a plasma display of the present invention is one in which the voltage, which is applied between the first electrode (x electrode) and the second electrode (Y electrode), is varied to make a difference in voltage in order to leave wall charges in the reset period, and to realize the above-mentioned object, the difference in the reset voltage, which is applied between the first electrode and the second electrode in the reset period, and that of the address voltage, which is applied between the first electrode and the second electrode in the address period, can be set to an arbitrary value for each subframe, and at least either one of the difference in the reset voltage or that in the address voltage differs from others at least in a subframe.
The difference in the reset voltage, which is applied between the first electrode and the second electrode in the reset period, affects the amount of wall charges to be left in the reset period. The sum of the address voltage difference and the voltage due to the wall charges is the effective voltage, which is applied between the first electrode and the second electrode in the address action. According to the present invention, the address voltage difference, which is applied between the first electrode and the second electrode in the address period, or the amount of wall charges to be left in the reset period, or both (i.e. the effective voltage), can be set to an optimum value for each subframe. Therefore, it is no longer necessary to take into account the time lag before the address discharge in the subframe, which used to be done, and the width of the scanning pulse can be narrowed in every subframe, resulting in a reduction in the time required for the address period.
The effective voltage in the address action is made larger in the subframe with a shorter sustain period than in that with a longer sustain period. When the frame reset period, in which a reset discharge is performed on the entire surface of the display frame, is provided at the beginning of the frame, the effective voltage in the address action is made larger in the subframe further from the frame reset period than in the subframe nearer to the frame reset period.
In addition, it may be a case in which the width of the scanning pulse, as well as the effective voltage in the address action, is set for each frame.
The driving method of the present invention is a method in which a desired amount of wall charges is left by changing the voltage at the end of a slope pulse, which is applied between the first electrode and the second electrode in the reset period. To change the voltage at the end, a circuit is employed in which the slope pulse is generated and the output voltage changes as time goes by, and the time of driving the circuit is controlled.